Programmable logic devices (PLDs) are integrated circuit devices containing a number of logic elements that can be selectively programmed to implement a wide variety of logic circuit designs. PLDs are commonly used in digital electronic systems together with other devices such as processors, bus drivers, and memory devices. For example, a field programmable gate array (FPGA) is a PLD that contains an array of logic blocks that represent the individual elements of the logic circuit design being implemented. Each logic block is programmably configured and the blocks are programmably interconnected to implement a user's desired logic functions and circuit design. Similarly, a complex PLD (CPLD) has a limited number of relatively large, user-programmable logic blocks—each of which is similar to a small PLD—that communicate with each other across an interconnect matrix.
In a PLD, input/output (I/O) terminals are used to provide data, control, address and clock signals to and from the configured logic blocks in the device. For example, memory controller logic blocks in FPGAs and CPLDs commonly read to and write from memory such as synchronous dynamic random access memory (SDRAM) or static random access memory (SRAM). The memory may be on the same integrated circuit device as the PLD or on a separate device. As used herein, an “I/O terminal” may refer to a terminal that is used as a unidirectional input terminal, exclusively as a unidirectional output terminal, or as a bidirectional terminal that can be configured to act either as an input or an output terminal at any one time. Since the size of a PLD circuit design depends on the number of logic blocks and the number of I/O terminals available, the use of bidirectional I/O terminals is often desirable to permit a given number of logic blocks to be implemented in smaller-sized device. Typically, the I/O terminals are physically implemented in an integrated circuit device as pins, pads, balls or some other type of terminal structure.
An I/O element circuit is often needed to provide an interface between an I/O terminal of a PLD logic array and an external device (or circuit) such as memory. The requirements of an I/O element circuit depend on the type of I/O terminal (i.e., input, output, or bidirectional) and on the I/O standard being used to communicate. Generally, a separate I/O element circuit is associated with each I/O terminal of the PLD. For bidirectional I/O terminals capable of being used for both reads and writes, the I/O element circuit typically provides an output enable (OE) signal that acts to selectively enable/disable write operations via the terminal. I/O element circuits, also referred to as I/O cells, can be programmably implemented as functional logic blocks, similar to the blocks in a PLD logic array.
Two I/O standards in particular, double data rate (DDR) and zero bus turnaround (ZBT), are frequently used in high speed data transfer applications. In the DDR I/O standard, data is clocked on both the rising and falling edge of a clock signal, effectively doubling the data rate of DDR SRAMs and SDRAMs. With the ZBT standard, synchronous fast SRAM devices are designed to provide 100% bus utilization by eliminating all idle clock cycles when turning the data bus around from a write operation to a read operation (or vice versa). This enables considerably faster operation in systems that require frequent and random read and write access, such as in networking and telecommunications applications.
In view of the above, there is a need for an I/O element circuit capable of allowing a logic device's I/O terminal to operate in high speed data modes, especially a DDR I/O mode and a ZBT I/O mode. It would be particularly desirable if such an I/O element circuit were capable of being programmably configured to operate in the different I/O modes.